Vogls: a Fast Interactive Full-timing Simulator for Pre-silicon Power Side-Channel Analysis
New pre-silicon simulator enables interactive power side-channel analysis during chip design, potentially catching leakage before tape-out — niche but relevant for hardware security research.
Summary written by editorial AI · Source link below
arXiv:2607.15782v1 Announce Type: new Abstract: Designing hardware circuits resistant to side-channel attacks increasingly relies on simulation to predict device leakage before fabrication. Current functional verification simulators are designed for extended correctness-checking runs and are ill-suited for producing large numbers of short trace collections with slight input variants needed for side-channel analysis. We present Vogls: an open-source Verilog simulator built for side-channel analy
External link — opens at arXiv Crypto & Security in a new tab.
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